Multi-Source Entity Extraction

H/W 설계 문서(PDF, PPT), Excel, Code 등 다양한 source에서 동일 entity를 자동으로 식별합니다. 아래 entity를 클릭하면 각 소스에서 추출된 위치가 하이라이트됩니다.

Extracted Entities

각 소스에서 추출된 entity 노드. 클릭하면 출처 위치가 하이라이트됩니다.

Block DiagramTRM PDF
Figure 2-2: Cortex®-A78 core overview DynamIQ™ Cluster Core 3* Core 2* Core 1* Core 0 RegisterRename InstructionIssue/Commit ExecutionPipeline InstructionDecode InstructionFetch MMU Load/Store L2 Memory System ETM GIC CPU Interface DSU Asynchronous Bridges DSU SCU and L3 * This core is optional
DocumentARM TRM

2.1 Core Pipeline Architecture

The Instruction Fetch unit fetches 32B/cycle from 64KB 4-way L1I. On L1I miss, fills come from the L2 Memory System.

The Execution Pipeline (8 ports: 2×ALU, 2×AGU, MAC, BR, FP, STD) dispatches memory ops to the Load/Store Unit (2LD+1ST, 64KB L1D).

The MMU provides I-TLB + D-TLB (1024 entries, 4KB~2MB pages). TLB miss triggers page table walk via L2.

L2 cache (256/512KB, 8-way, 64B line) serves L1I/L1D/PTW. L2 miss → DSU L3 via ACE.

ETM (ETMv4) traces via ATB. GIC CPU IF (GICv3) handles IRQ masking.

Verilog RTLSystemVerilog
IP-XACT Register MapXML · IEEE 1685
cortex_a78_subsystem.xml<spirit:component>
spirit:addressBlock
spirit:memoryMap
spirit:busIF
#spirit:namebaseAddressrangeregistersbusIF
1MMU_TLBSysRegAArch64TTBR0_EL1, TCR_EL1—
2L2_CacheSysRegInternalL2CTLR_EL1ACE
3GIC_CPU_IF0x0000_000064KBICC_IAR1_EL1AXI4
4ETMv40x0004_00004KBTRCPRGCTLRAPB3
5DSU_AE0x0008_000064KBCLUSTERPWRCTLRACE-Lite
6DSU_CHI§4.264KBCLUSTERPWRCTLRCHI
6Exec_PipeN/A———
7IFUN/A———
8LSUN/A———

Relation Extraction via Link Prediction

Relation type prompt와 entity가 마킹된 문장을 모델에 입력하여, entity pair 간 가장 적합한 relation을 예측합니다.

* embedding: 텍스트의 의미를 model이 이해할 수 있는 형태로 표현한 것
Relation Types Prompt (zero-shot)
Input Sentence with Named Entities
↓
Language Model
Relation Type Embeddings
×
Entity Pair Embeddings
↓
↓
Extracted Triple Set

Knowledge Graph Construction

Link Prediction에서 추출된 relation triple들을 순차적으로 합쳐 Knowledge Graph를 구성합니다. 동일 entity는 자동 병합되며, 충돌하는 relation은 탐지됩니다.

0 / 6 triples
Triple Queue
엣지를 클릭해보세요 — 출처가 표시됩니다

Conflict Resolution

Knowledge Graph 구축 중 감지된 relation 충돌을 confidence score 기반 분석과 LLM 추천으로 해결합니다.

CONFLICT #1 L2 ↔ DSU 동일 entity pair에 상호 배타적 relation 감지
L2 DSU
A
B
AI
Conflict Analyzer
MMU IFU L2 DSU page_table_walk_via l1i_miss_filled_by forwards_miss_via_ace forwards_miss_via_chi
MMU page_table_walk_via L2
출처 : ARM Cortex-A78 TRM §2.5 — "On TLB miss, the MMU performs hardware page table walks that access the L2 Cache for translation table entries."
IFU l1i_miss_filled_by L2
출처 : ARM Cortex-A78 TRM §2.2 — "L1I cache misses from the Instruction Fetch unit are serviced by the L2 Memory System."

Downstream Task

구성된 Knowledge Graph를 활용한 충돌 탐지, QA 등. (구현 예정)